1. Field of the Invention
The present invention generally relates to the field of semiconductors. More particularly, the invention relates to transistor semiconductor structures.
2. Background Art
MOS (Metal Oxide Semiconductor) transistors, such as Lateral Diffusion Metal Oxide Semiconductor (LDMOS) transistors, can be utilized as power transistors in high voltage switches and power amplifiers in cell phones and other wireless communication devices, as well as other types of applications that require a high power transistor. In a MOS transistor, such as an LDMOS transistor, it is desirable to provide a high breakdown voltage and a low on-resistance (Rdson), which refers to the source-to-drain resistance of the transistor when it is turned on. However, channel length of a MOS transistor, such as an LDMOS transistor, can affect the breakdown voltage and the on-resistance of the transistor. Thus, during transistor fabrication, it is important to precisely control the channel length of a MOS transistor, such as an LDMOS transistor.
In a conventional LDMOS transistor, a gate can be formed over a first well and an adjacent second well, a source region can be formed in the first well adjacent to a sidewall of the gate, and a drain region can be formed in the second well, where the drain region is spaced apart from an opposing sidewall of the gate. In the convention LDMOS transistor, a channel length can be defined by the distance between the source region and the second well.
Although the source region can be self-aligned to the gate, the second well is typically formed by a mask, which is not self-aligned. Consequently, mask alignment error can cause the channel length to vary from run to run during fabrication of the conventional LDMOS transistor. As a result of the run-to-run variation in channel length, the breakdown voltage and the on-resistance of the conventional LDMOS transistor can also vary from run to run, which is undesirable.